Circuits comprising an amplifier and buffer find many applications in modern electronic devices. For example, voltage regulators based on such circuitry are used to supply a constant voltage source from an unregulated or regulated higher voltage supply. Low dropout (LDO) linear regulators are designed to allow a small voltage drop between the input supply and the regulated output voltage. LDOs thus decrease the headroom requirement and also increase power efficiency compared to linear regulators with high dropout architectures.
FIG. 7 shows a typical architecture for a low dropout linear regulator 10. The input stage is a differential gain stage consisting of a transconductance (gm) amplifier 11 driving a high impedance node (VG) with a resistance RO in parallel with a capacitance C1. The VG node is where the majority of the regulator's gain is established. Following the input gain stage is a buffer amplifier 13 to drive the high capacitive node of a pass element. For this architecture, a PMOS transistor 15 is used as the pass element to deliver current from the input supply to the regulator output. A resistor divider, RF1 and RF2, feeds back a divided voltage of the output to the non-inverting input terminal of the gm amplifier 11. This feedback regulates the output voltage to some multiple of VREF depending on the ratio of the feedback resistors. The LDO output (VOUT) is bypassed by an output capacitor COUT.
Some of the specific challenges regarding the design of LDOs relate to its compensation. The frequency of the output pole (POUT) directly depends on the load current and is equal to 1/(2π*RO,PMOS*CO). RO,PMOS is the drain output resistance of the PMOS transistor pass device 15 and equals VA/ILOAD, where VA is the transistor Early voltage, and ILOAD is the output load current. Thus, POUT can swing several decades depending on the load current swing, making the placement of the pole at VG (PG) critical. If the frequencies of PG and POUT lie too close together below crossover frequency, instability can occur.
One compensation strategy is to make POUT the dominant pole. The non-dominant pole PG, therefore, must lie beyond the maximum frequency of POUT by at least the gain of the regulator for ample phase margin. This can lead to high operating currents, and often low loop gain to ensure PG is beyond crossover. Increasing the output capacitor value to guarantee that POUT is at low enough frequencies for all load currents also can be unattractive due to increased cost and solution size.
Another strategy is to make PG the dominant pole by adding a compensating capacitor at VG. POUT, therefore, must either lie beyond the crossover frequency, or a zero must be inserted (usually in the form of capacitor ESR) to counter the pole before crossover. The first case defines a minimum frequency requirement for POUT, placing constraints on the minimum load current and maximum output capacitor value. These constraints can be undesirable as they generally require significant quiescent load current and typically have poor transient response. The second case puts specific constraints on the type of output capacitor, and again requires a broadband PG pole beyond the output zero. These constraints can be undesirable for size, power consumption, cost, and transient response reasons.